> On Tue, 6 May 1997, Kyle Platts wrote:
>
> > If you have 2 CSU/DSU's set to either both provide or both receive
> > timing, you will see slips as a result of the 2 closck fighting each
> > other. The quality of the clock determines how many slips in a certain
> > time period you could expect to receive. For instance a stratum 2 clock
> > is more stable (less slips) than a stratum 3.
>
> The thing is, BellSouth has recently told me (I don't know how true it
> is...but it came from a troubleshooter at the local CO) that they never
> provide clock on PTP T1's. I have a T1 customer who (if this is true) has
> been misconfigured with both CSU/DSU's set to get clock from the loop for
> a year with no problems...until yesterday when the Pairgain at their end
Were they keeping stats on the line? Are all their error counters showing
zero? I don't think so. The only thing that might save them (assuming
its misconfigured) is that T1 circuits are designed to operate at 1.5MHz
and even with no clock they will migrate to a freq. close to this. So
with a constant data stream helping the circuit freewheel at close to
1.5MHz, their error rates may have been low enough that they never
noticed. And I guess they just got lucky. But they can't have had zero
error counts! Science just won't allow it!
> of the circuit fried. I assume that's totally unrelated. I've set the
> CSU/DSU at my end of their T1 to internal/master clock, and the line seems
> just as stable.
>
Al Hopper Logical Approach Inc, Plano, TX. al@logical-approach.com
(972)-379-2133 or (972)-849-5765. Fax 972-379-2134